CMOS integrated circuits, such as memory or mixed signal circuits, typically require a specified and stable reference voltage to insure proper circuit operation. In the design of integrated circuits, a reference voltage is typically generated internally on the integrated circuit, or “on-chip,” for use by circuitry on the integrated circuit. The internally generated reference voltage needs to be stable and accurate to be useful. Due to fabrication process variations, the voltage value generated by an internal or on-chip reference voltage source often varies from chip to chip. To set the desired operating point for the internal reference voltage source, adjustments to the integrated circuit is performed to fine tune the internal reference voltage source to the desired operating point. The adjustment process is referred to as trimming and the adjustments are typically made through trim bits that are stored on the integrated circuit to set the desired operating point of the internal reference voltage source.
Conventional trimming methods involve testing the integrated circuit on a tester to find the set of trim bits that gives the desired reference voltage value. FIG. 1 is a schematic diagram illustrating a conventional trimming method applied to an integrated circuit. Referring to FIG. 1, an integrated circuit 1 is a memory integrated circuit and includes memory circuitry 2 for its native function. The memory circuitry 2 uses a reference voltage Vrefi (node 6) for some of its operations. An internal or on-chip reference voltage source 4 generates the reference voltage Vrefi for the memory circuitry 2. The internal reference voltage source 4 typically receives the power supply voltage Vdd to generate the reference voltage Vrefi. The reference voltage Vrefi generated by the reference voltage source 4 may vary from chip to chip due to process variations. Because accuracy of the reference voltage Vrefi is important to the operation of the memory circuitry 2, the integrated circuit 1 provides circuitry to trim the reference voltage source 4 to the desired reference voltage level. In particular, the reference voltage source 4 is configured to receive a set of trim bits 12 which is used to trim or adjust the voltage value generated by the reference voltage source.
The conventional trimming method for the internal reference voltage source 4 is performed as follows. The integrated circuit is placed on the tester and put in a test mode. A test program is designed to supply a trim code sequence to the integrated circuit. The tester applies the trim code sequence to the trim bits 12 of the integrated circuit. Meanwhile, the reference voltage Vrefi generated by the internal reference voltage source 4 is coupled to a voltage measurement port on the tester, such as through an input/output pin of the integrated circuit 1, to be measured. With each trim code being applied, the reference voltage source 4 generates a different reference voltage value. The tester compares the reference voltage generated from the reference voltage source 4 to a target voltage at the tester's voltage measurement port. When the target voltage level is detected, the tester writes or programs the trim code corresponding to the target voltage level to the integrated circuit. More specifically, the trim code is stored in a non-volatile memory 8 of the integrated circuit for use in the normal operation of the integrated circuit. When the integrated circuit 1 is applied in its normal operation, the internal reference voltage source generates a reference voltage having the desired target voltage value based on the stored trim code. However, the conventional trimming methods can be time consuming because the reference voltage generated by the internal reference voltage source must be measured by the voltage measurement units on the tester. The tester voltage measurement units often have a long settling time so that voltage measurements at the tester can take a long time.